DIODELESS_PEAK_HOLD_CIRCUIT

Published:2009/6/23 3:38:00 Author:Jessie | From:SeekIC

The input pulse is fed into the sample-and-hold amplifier (an inexpensive AD582), as well as the comparator U3. The SHA's output also is fed into the comparator. If the input pulse is higher in am-plitude than the SHA's output, the comparator output goes low and the 4538 one-shot produces a l0-ps pulse that is fed back to cause the SHA to sample and then hold the voltage. Subsequent input voltages that are less than the held value won't cause the one-shot to fire again.Gates U4A and U4B are used to inhibit the sampling when necessary. Gates U4C and U4D, at the one-shot's output, can force the AD 582 into the sample mode. This feature is useful to reset the output to zero by forcing a sample when the input to the AD582 is zero. The polarity of the peak-hold circuit can be easily changed from positive-to-negative peak hold by reversing the inputs of the comparator.



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