Published:2011/7/13 19:55:00 Author:leo | Keyword: Simple transistor test circuit, P channel FET | From:SeekIC
As the picture a and b show, it is a simple transistor test circuit. The picture13(a) shows a FET test circuit. This circuit is mainly used to test FET pinch-off voltage UP and grid-source voltage UGS. In the circuit, VT is the FET to be tested, and A1 can form servo circuit whose output controls reversal phase input terminal potential and makes it become zero. Voltage-stabilizing diode VD3 and VD4 can produce voltage of±9V and clamp-on the grid potential of VT. R5 is the current limiting resistance which controls VT grid potential current and makes it under the set value. When S2 is connected to 1, VT grid potential voltage is higher than clamp-on voltage and A1 output is negative to the N channel FET while positive to the P channel FET.
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