SWITCHED_CAPACITOR_ADC

Published:2009/7/5 20:57:00 Author:May | From:SeekIC

The CMOS comparator in the successive-approximation system determines each bit by examining the charge on a series of binary-weighted capacitors. In the first phase of the conversion process, the analog input is sampled by closing switch SC and all ST switches, and by simultaneously charging all the capacitors to the input voltage. In the next phase of the conversion process, all ST and SC switches are opened and the comparator begins identifying bits by identifying the charge on each capacitor relative to the reference voltage. In the switching sequence, all 8 capacitors are examined separately until all 8 bits are identified, and then the charge-convert sequence is repeated. In the first step of the conversion phase, the comparator looks at the first capacitor (binary weight = 128). One pole of the capacitor is switched to the reference voltage, and the equivalent poles of all the other capacitors on the ladder are switched to ground. If the voltage at the summing node is greater than the trip point of the comparator-approximately 1/2 the reference voltage, a bit is placed in the output register, and the 128-weight capacitor is switched to ground. If the voltage at the summing node is less than the trip point of the comparator, this 128-weight capacitor remains connected to the reference input through the remainder of the capacitor-sampling (bit-counting) process. The process is repeated for the 64-weight capacitor, the 32-weight capacitor, and so forth down the line, until all bits are tested. With each step of the capacitor-sampling process, the initial charge is redistributed among the capacitors. The conversion process is successive-approximation, but relies on charge shifting rather than a successive-approximation register-and reference d/a-to count and weigh the bits from MSB to LSB.



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