Synopsys announced the latest Synplify FPGA synthesis tools

Published:2012/4/5 0:55:00 Author:Ecco From:SeekIC

The Synopsys’ engineers have developed Synplify Premier FPGA synthesis tools. The Synplify 2012.03 products include improved synthesis algorithms that accelerate runtime by up to 30 percent. What’s more, the Synplify Premier software is improved with a new continue-on-error. It is especially useful for FPGA-based prototypers who may not be as familiar with the source HDL code. The tool helps enhance speed of validation process and reduce development time for users.

The new Synplify 2012.03 software release offers FPGA designers significantly shorter design cycles. The continue-on-error feature addresses FPGA-based prototypers’ need for fast turnaround time by eliminating the need to address errors. Instead of stopping with each error, the tool continues compilation after an error is found, generating a report of all the errors encountered so that they can be addressed at once, without re-compiling between each fix. To further simplify the process for ASIC prototypers, the Synplify synthesis tool has a datapath latch conversion feature to automatically convert an ASIC design to an FPGA implementation, making it possible for the designer to use a single set of source files to implement the FPGA-based prototype.

Further more, the new Synplify Premier software release further automates the process of building high reliability and fault tolerance into an FPGA design. And it uses a combination of advanced features including selective triple modular redundancy (TMR), Hamming-3 encoding and fault-tolerant error correcting code (ECC) memories for detection and correction of soft errors.

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