The Cooperation between Samsung and Cadence Benefits each other

Published:2012/2/7 2:46:00 Author:Li xiao na From:SeekIC

The cooperation between Samsung Electronics’ foundry business and Cadence allows developing a design-for-manufacturing (DFM) infrastructure. This involves the development of “in-design” and signoff DFM flows to deal with physical signoff and electrical variability optimisation for 32-, 28- and 20nm system-on-chip (SoC) designs.

The goal of the firms if to solve both random and systematic yield issues with a foundry option for advanced-node designs built on the Cadence Encounter digital and Cadence Virtuoso custom/analog implementation solutions. Vice president of Samsung Electronics’ Infrastructure Design Centre points out that people’s demand of design flow becomes higher and higher when they are expanding customer base at advanced process nodes.

What is more, Samsung Electronics has gained numerous benefits that can help it to reduce risk and speeding time to market after teaming with Cadence. As semiconductor manufacturing complexity increases at the 32- and 28nm process nodes there is an impact on design cycle time and time to yield compared to previous nodes. In order to perform effective and accurate systematic failure analysis, Samsung Foundry can use the hierarchical design approach and pattern.

Samsung will continue extend the advanced DFM flow to 20 nanometers in the following day after the success at 32 and 28 nanometers with Cadence. The Cadence Pattern Classification technology of DFM flows allows it to classify the yield detractor patterns into practical pattern libraries. With this infrastructure, the customers are able to leverage the in-design and sign off pattern matching with automated fixing flows in Encounter and Virtuoso. In the process of cooperation, Cadence also continues to achieve momentum as the advantages of in-design DFM become increasingly evident.

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