TSMC Plans to Announce 3-D IC Assembly Service

Published:2012/2/3 1:00:00 Author:Phyllis From:SeekIC

Taiwan Semiconductor Manufacturing Company (TSMC) plans to announce 3-D IC assembly service as a general offering at the beginning of 2013.

Called COWOS internally, the technology is standing for chip on wafer on substrate. The company has one year to get all physical design kits and EDA support in place to allow customers to design with COWOS.

TSMC is already working with companies such as Xilinx on the use of silicon interposer layers to carry multiple die. These 3-D customers will continue using external packaging partnerships if they choose. However, when the 3-D IC assembly service is offered TSMC plans that for most customers the 3-D assembly is done by TSMC.

A number of mobile applications processor companies, including Qualcomm and ST-Ericsson, are known to be investigating 3-D IC packaging specifically to make use of wide I/O DRAM which is expected to relieve bandwidth issues and reduced energy consumption.

The use of multiple die in components, which already commonplace in multi-chip package (MCP) memory for mobile applications, would likely change the nature of IC logic and SoC design. It would allow different functions to be developed on different optimized processes and brought together making use of through silicon vias (TSVs) created in thinned wafers. TSMC is offering a TSV-first approach to 3-D IC stacking.

Large amounts of non-volatile memory or wide I/O DRAM could be introduced into application processors without having to include such technologies in leading-edge logic processes. It is believed that there is a good way of achieving performance while saving power and real-estate. Developers could stack an embedded flash device in 40-nm on an application processor in 28- or 20-nm.

Whether TSMC is prepared to assemble die from different vendors such as memory die from specialist manufacturers as part of its 3-D IC assembly service remains unclear.

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