TRAMS Analyze the 10 nm Statistical Variability

Published:2011/11/3 1:42:00 Author:Li xiao na From:SeekIC

The TRAMS has analyzed the statistical variability in a 10 nm channel length finfet on SOI substrate by the advanced statistical TCAD simulation, which can be the important milestone of this team. Intel, Imec, Glasgow University and the Universitat Politècnica de Catalunya (UPC) constitute the TRAMS consortium. The Glasgow University team is responsible for the device design and simulation. Professor Asen Asenov, who developed the simulation software lead the team of this university. The software utilizes the grid computing linking thousands of computers to simulate the behaviour of billions of individual transistors in an IC.

In order to meet the requirements of 11 nm CMOS technology generation, the TRAMS finfets are developed. The simulations have been carried out using unique simulation technology available to the project. The major unknown sources of statistical variability and reliability are included in the project, such as random discrete dopants, the gate and the fin line edge roughness, the metal gate variability and bias temperature instability effects.

The TRAMS partners have gained the results of the physical simulations in accurate statistical compact models. These models are being used to evaluate the impact of statistical FinFET variability on 11nm embedded memory design and to develop circuit and system countermeasures. Originally, TRAMS aimed to investigate the impact of the statistical NanoCMOS variability on tera-scale embedded SRAM memories.

The main obstacle to scaling and integration is the statistical variability. This problem can be solved by slowing supply voltage scaling, especially for SRAM, and threatening the continuation of area scaling.

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