The ISE Design Suite 13.3 Developed by Xilinx

Published:2011/11/2 2:16:00 Author:Li xiao na From:SeekIC

The ISE Design Suite 13.3 is released by the Xilinx, which features new capabilities. It is designed for the DSP designers to implement bit-accurate single, double and full custom precision floating-point math operations in designs. It aims to the applications of wireless, medical, aerospace and defense, high-performance computing and video. Through System Generator for DSP, the flow is available, and the flow makes use of the Xilinx Floating-Point Operator IP LogiCORE.

Moreover, Xilinx is able to guarantee that the simulation model will match the hardware implementation, because only System Generator for DSP provides developers with a bit accurate solution. Xilinx 7 series 28nm FPGAs can send up to 1.33 teraflops of single-precision floating-point performance on one device, which drives the demand for an easy-to-use design flow that delivers hand crafted results. With the Xilinx Floating-Point Operator core, a range of floating-point arithmetic operations are available. When the core is generated through the CORE Generator tool and now System Generator, and each operation variant has a common AXI-4 streaming interface, the operation is specified.

To implement a floating-point design in a Xilinx FPGA was possible in the past, but there were challenges to for the developers, for example, the design flow needed an understanding of VHDL or Verilog and simulation. Now, this problem can be solved by the ISE Design Suite 13.3. Their design can meet their needs by leveraging the simulation capabilities in the MathWorks’ Simulink tool. The Red Hat Enterprise Linux 6 is also added to the ISE Design Suite 13.3. Enhancements to Plug-and-Play IP and device support for 7 series devices are contained in the whole editions.

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