Published:2011/9/26 1:29:00 Author:Li xiao na From:SeekIC
The demand for the variation-aware custom IC becomes high when the process geometries continue to shrink. The electronic design community has recognized this fact.
Many parts of the custom IC design will be influenced y the variation, such as analog/mixed-signal, RF, I/O, memory and standard cell libraries. It results in actual silicon performance and yield differing from that predicted in simulation. Many different elements can cause the variation, such as the random effects, environmental issues and layout dependent effects.
At the sub-micron level, engineers mainly concern the variation either by over-margining or under-designing. Over-margining leaves significant performance, power and area on the table. Under-designing results in yield failures. These methods will be very costly. The variation problems are belonging to the process-voltage-temperature (PVT), Monte Carlo statistical, high-sigma Monte Carlo statistical or proximity issues.
Due to the increasing number of corners required to bound the effects of variation, the PVT corner design is slow. Guessing which PVT concerns will lose accuracies. Moreover, the PVT corners don’t always reflect the actual worst-case corners, so a closer look at random variation is in need. The Monte Carlo analysis always needs so much time and money. What is more, the accuracy will be influence when we reduce the number of samples to speed up Monte Carlo analysis.
The proximity effects design involves trading off costly schematic and layout iterations against over-designing and blowing out area, which can solve the problem that using an accurate model of variation and having the rapid design iterations.
Some techniques can be used without disrupting existing, standard design flows, for example, one technique which contains optimal sampling and design-specific corners can be used to avoid the trade-off of accuracy versus the speed of results; Optimal sampling employs efficient algorithms; design-specific corners can be simulated quickly to accurately capture boundaries.
Reprinted Url Of This Article: http://www.seekic.com/blog/IndustryNews/2011/09/26/Techniques_to_Deal_with_the_sub_micron_design_Variation.html
Print this Page | Comments | Reading(241)
Author:Ecco Reading(32819)
Author:Ecco Reading(3526)
Author:Ecco Reading(3246)
Author:Ecco Reading(3801)
Author:Ecco Reading(5331)
Author:Ecco Reading(3315)
Author:Ecco Reading(3462)
Author:Ecco Reading(3604)
Author:Ecco Reading(4009)
Author:Ecco Reading(3807)
Author:Ecco Reading(3748)
Author:Ecco Reading(3780)
Author:Ecco Reading(6094)
Author:Ecco Reading(3764)
Author:Ecco Reading(4579)