Signal Integrity Problems Emerge in the Task

Published:2011/9/26 2:12:00 Author:Phyllis From:SeekIC

The maintenance of signal quality at 10-Gbits/sec speeds is far more difficult than in the 1-to-3 Gbits/sec range. To initiating the first designs in the 10-Gbits/sec realm, one has to confront new realities that will dominate signal-quality issues, like backplanes and network interfaces move into that speed range.

Discontinuities are encountered not only at the level of the individual device but also at the level of the board trace, which influence both board layout and the choice of substrate materials.

When the task is considered at both board and device levels at once, a few common sources of potential signal integrity problems emerge. First is the PCB Layout. Characteristics of physical design such as the use of via stubs can have a significant impact on the integrity of data channels operating at tens of gigabits per second. AC-coupling difficulties can be aggravated by the scrambling methods used in advanced designs. As standards have shifted from 8B/10B encoding to 66B/64B, such scrambling is an order-of-magnitude more difficult to address. Design discipline at both device and board level must be practiced, along with real-time monitoring of eye patterns.

Second is about plane discontinuities. Discontinuities can be handled through proper termination of signals and a simple, straightforward board layout. Ground vias should be spaced appropriately to prevent waveguide modes from occurring, due to a large number of vias along signal traces, and sparse allocation of ground vias even in open areas.

The third one is edge rate design techniques. This is an issue related to specific devices used in a design, which can have an impact on board-level layout. Fast output edges and rise times can eliminate or lessen the need for pre-emphasis or de-emphasis, and designs without pre-emphasis or de-emphasis can offer less crosstalk and lower power dissipation. The consideration of edge rates allows us to segue into signal integrity issues more appropriately considered at the device level.

The fourth problem is transmitting equalization. Pre-emphasis, de-emphasis and pre-compensation can be performed in the digital domain by using clocked drivers or, in an analog fashion, using time-domain-based multiple-decay filters.

Next one is receive equalization: Multi-stage analog input-signal equalization may appear more complex than simple single-stage designs, but high-frequency designs require nonlinear input equalization. Careful planning in such designs can allow the use of low-cost PCB materials such as FR4.

Advanced equalization in both transmit and receive chains can take advantage of retimer signal -analog equalization to compensate for linear high-frequency loss, and the availability of digital equalizers or Decision Feedback Equalizers (DFE) in retime circuits and ICs can help combat crosstalk and reflections.

One factor that is not often recognized is that waveform analysis becomes a much harder task as more devices in high-speed design use equalization. Many semiconductor vendors are turning to embedded-probe and test-point technologies for high-speed line cards, and the most advanced designs offer full embedded-waveform analysis accessible from the chip level.

Reprinted Url Of This Article: http://www.seekic.com/blog/IndustryNews/2011/09/26/Signal_Integrity_Problems_Emerge_in_the_Task.html

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