The Suitable Way to Test 3D ICs

Published:2011/9/21 23:02:00 Author:Li xiao na From:SeekIC

Semiconductor design begins to use the 3D IC package. This can reduce the package size and power consumption while increasing performance due to the improved physical characteristics of the very small TSV connections compared to the much larger bond wires used in traditional packaging. However, the test process will become more complicated, so the 3D ICs need new method to solve this problem.

How to test the TSV connections between the stacked memory and logic die is a new challenge, because there is no external access to TSVs, making the use of automatic test equipment difficult at best.

The built-in self-test (BIST) techniques, which are used to test embedded memories within system-on-chip (SoC) devices, become the new solution to solve the above problems. In this approach to 3D test, a BIST engine is integrated into the logic die and communicates to the TSV-based memory bus that connects the logic die to the memory.

Two different techniques to existing embedded memory BIST approaches are necessary for this approach to work.

One is the architecture which makes the BIST engine to communicate to a memory bus rather than directly to individual memories possible. Because multiple memories may be stacked within the 3D IC, but mostly to allow the BIST engine to test the memory bus itself, and hence the TSV connections, rather than just the memories, this is very important.

The other essential technique is the fully run-time programmable. With only the standard IEEE 1149.1 JTAG test interface, the BIST engine can be programmed in silicon to adapt to different memory counts, types and sizes stacked on top of the logic die.

All in all, the engineers want to the test of 3D ICs without delay or risk, so the way to test between memory logic die is the suitable solution.

Reprinted Url Of This Article: http://www.seekic.com/blog/IndustryNews/2011/09/21/The_Suitable_Way_to_Test_3D_ICs.html

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