The International Electron Device Meeting in 2011

Published:2011/9/21 2:17:00 Author:Li xiao na From:SeekIC

The International Electron Device Meeting was a forum for chipmaker to find out the fastest, densest processes before. However, in the recent years, the focal point has changed from the peak speed to a tradeoff between power and performance, because several paper reflecting the need to move away from traditional transistor metrics.

In the past, an method, which can look more at parasitics such as drain-induced barrier lowering (DIBL), had greater effect on performance in all but the fastest, most power-hungry logic circuits. In order to simulation to tune devices for real-world circuits rather than ultimate, single-device performance, NXP Semiconductor has cooperated with TSMC for decades of years. The 2011 IEDM is based on this kind of work.

Members of IBM’s TJ Watson Research Centre list some new elements what they believe is a necessary new optimisation constraint for device evaluation: energy x power density can better reflect actual design goals and compromises. People from the Massachusetts Institute of Technology try to show that the performance benefits at the circuit level depend strongly on the target applications and load scenarios. P/N width ratio, supply ratios and off-state current per unit width must be optimised for the target application and load scenario.

Actually, a number of experimental processes will be mentioned in the conference, such as Intel’s latest foray into using III-V materials to produce high-speed, low-power transistors. tri-gate FinFET-type quantum-well indium gallium arsenide MOSFETs with 30nm gates will be displayed, which can deliver the best electrostatic performance of any III-V MOSFET. The subthreshold slope of 66mV/decade will also be exhibited by Long-channel devices.

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