Microprocessor with transactional memory

Published:2011/9/1 2:44:00 Author:Phyllis From:SeekIC

Multicore chips researchers have studied for years about a new feature of commercial microprocessor. IBM has become the first company to ship such microprocessor with transactional memory.

This new feature will applied in the BlueGene/Q processor used in the Sequoia supercomputer IBM is building at present and it will complete in 2012. The super could become one of the most powerful systems in the world after that.

With the transactional memory, related tasks can be organized into one big job for more efficient processing. The transactional memory replaces the current practice of locking data until a complex job is done, an approach that can slow down other computer operations.

Researchers have studied transactional memory for several years. IBM only implemented transactional memory within the confines of a single chip using a tagging scheme on the chip’s level-two cache memory. The tags are used to detect any load/store conflicts in data to be used in a so-called atomic transaction scheduled by the computer.

Thanks to its use of fast on-chip memory, the IBM approach lowers latency when compared to traditional locking schemes even under conditions where there is high data contention.

Observers said the IBM work was sound but could not be widely used by other designers. A more useful approach would be to implement transactional memory among a broad group of processors linked in a complex cache-coherent scheme, they said.

Programmers using the IBM supercomputer are some of the most sophisticated software coders in the world, and they use a very limited set of applications. As such, they are good candidates to test out transactional memory.

The IBM chip uses 18 cores, one just to process operating system tasks and another held in reserve as a spare. The cores are a custom circuit design based on the PowerEN core used in an IBM communications chip.

The rest of the BlueGene/Q processor was designed in an ASIC process given expectations for relatively low volume sales. The supercomputer may use as many as 100,000 of the chips. Running at 1.6 GHz, they deliver 204 Gflops at 55W, use 1.47 billion transistors and measure 19 x 19 mm.

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