The Evolution Time of 100 GbE is coming

Published:2011/8/31 1:57:00 Author:Phyllis From:SeekIC

For data center and service provider networks that are struggling to satisfy the global economy’s relentless hunger for more bandwidth, the realization of cost-effective and energy-efficient 100 Gigabit Ethernet (100 GbE) links will be an essential step. For the first time, they are implemented as large, power-hungry, niche market products that use the steady improvements in commercial CMOS technology to produce ICs required to migrate to more compact, low-power industry-standard transceiver modules required for mainstream applications.

At present, the high-speed SerDes function of 100 GbE transceiver are widely used in exotic silicon-germanium (SiGe) processes to innovative low-power designs that can be economically fabricated using mainstream commercial CMOS processes. The first step in this evolution is to extract this function from its present implementation. The second step on this path is to improve the signal integrity of the SerDes so it can be moved out of the 100 GbE transceiver module and onto the line card.

This evolution can not move on without the support of high-speed, low-power CMOS architectures which provide complete solutions for the physical layer ICs inside the transceiver module and on the line card. With this technology, the next generation 100 GbE systems will be able to offer up to 10 times higher port density while reducing transceiver power consumption by more than 50%.

The 100 Gbps Ethernet standard and the technologies that will support it are being developed in direct response to the seemingly endless growth in bandwidth demand which threatens to overtake the current capabilities of data centers, service providers and enterprise networks. As server-to-switch links migrate from 1 GbE to 10 GbE, the switches and router links that they connect are being forced to move from 10 GbE to 100 GbE. In order to accommodate the rapidly-growing traffic within the tight confines of a data center or cloud compute facility, the capacity of the line cards within those switches and routers will have to increase from today’s 480 Gbps levels, to capacities as much as 3 Tb/s per Line card and 30-40 Tb/s per chassis in the next several years.

CFP modules will play an important role in paving the way for mass-adoption of 100 GbE technologies, but they must be quickly followed by succeeding generations of more compact, more affordable and more power-efficient products that can achieve the line densities required for mainstream commercial applications.

Regardless of module type, the Retimer/PHY element can be fabricated in either SiGe or CMOS. Due to its complexity and size, any energy or cost savings that can be realized in this element has a large effect on the overall solution.

CMOS is the technology of choice for developing a low-power SerDes transceiver capable of supporting the 25Gbps data streams needed in to drive the optical modules used in the next-generation 100 GbE equipment. Line card and optical module manufacturers using CMOS products will also benefit from the large community of competing foundries which engage in aggressive pricing strategies and rapid adoption of ever-smaller process nodes that deliver successively lower per-chip costs, reduced operating voltages, and lower power consumption.

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